XCF32PFSG48C

IC PROM SRL/PAR 1.8V 32M 48CSBGA

Features

• In-System Programmable PROMs for Configuration of Xilinx® FPGAs

• Low-Power Advanced CMOS NOR Flash Process

• Endurance of 20,000 Program/Erase Cycles

• Operation over Full Industrial Temperature Range (–40°C to +85°C)

• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing

• JTAG Command Initiation of Standard FPGA Configuration

• Cascadable for Storing Longer or Multiple Bitstreams

• Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)

• I/O Pins Compatible with Voltage Levels Ranging From 1.8V to 3.3V

• Design Support Using the Xilinx ISE® Alliance and Foundation™ Software Packages

• XCF01S/XCF02S/XCF04S

• 3.3V Supply Voltage

• Serial FPGA Configuration Interface

• Available in Small-Footprint VO20 and VOG20 Packages

• XCF08P/XCF16P/XCF32P

• 1.8V Supply Voltage

• Serial or Parallel FPGA Configuration Interface

• Available in Small-Footprint VOG48, FS48, and FSG48 Packages

• Design Revision Technology Enables Storing and Accessing Multiple Design Revisions for Configuration

• Built-In Data Decompressor Compatible with Xilinx Advanced Compression Technology

Description

• In-System Programmable PROMs for Configuration of Xilinx® FPGAs

• Low-Power Advanced CMOS NOR Flash Process

• Endurance of 20,000 Program/Erase Cycles

• Operation over Full Industrial Temperature Range (–40°C to +85°C)

• IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing

• JTAG Command Initiation of Standard FPGA Configuration

• Cascadable for Storing Longer or Multiple Bitstreams

• Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)

• I/O Pins Compatible with Voltage Levels Ranging From 1.8V to 3.3V

• Design Support Using the Xilinx ISE® Alliance and Foundation™ Software Packages

• XCF01S/XCF02S/XCF04S

• 3.3V Supply Voltage

• Serial FPGA Configuration Interface

• Available in Small-Footprint VO20 and VOG20 Packages

• XCF08P/XCF16P/XCF32P

• 1.8V Supply Voltage

• Serial or Parallel FPGA Configuration Interface

• Available in Small-Footprint VOG48, FS48, and FSG48 Packages

• Design Revision Technology Enables Storing and Accessing Multiple Design Revisions for Configuration

• Built-In Data Decompressor Compatible with Xilinx Advanced Compression Technology

Description

Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Mb densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4 Mb, 2 Mb, and 1 Mb PROMs that support Master Serial and Slave Serial FPGA configuration modes (Figure 1, page 2). The XCFxxP version includes 32 Mb, 16 Mb, and 8 Mb PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes (Figure 2, page 2).

When driven from a stable, external clock, the PROMs can output data at rates up to 33 MHz. Refer to "AC Electrical Characteristics," page 16 for timing considerations.

A summary of the Platform Flash PROM family members and supported features is shown in Table 1.

When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. With CF short access time after CE High, a and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each rising clock edge. The FPGA generates the appropriate number of clock pulses to complete the configuration.

When the FPGA is in Slave Serial mode, the PROM and the FPGA are both clocked by an external clock source, or optionally, for the XCFxxP PROM only, the PROM can be used to drive the FPGA’s configuration clock.

The XCFxxP version of the Platform Flash PROM also supports Master SelectMAP and Slave SelectMAP (or Slave Parallel) FPGA configuration modes. When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM. When the FPGA is in Slave SelectMAP Mode, either an external oscillator generates the configuration clock that drives the PROM and the FPGA, or optionally, the XCFxxP PROM can be used to drive the FPGA’s configuration clock. With BUSY Low and CF High, after CE and OE are enabled, data is available on the PROMs DATA (D0-D7) pins. New data is available a short access time after each rising clock edge. The data is clocked into the FPGA on the following rising edge of the CCLK. A free-running oscillator can be used in the Slave Parallel/Slave SelectMAP mode.

The XCFxxP version of the Platform Flash PROM provides additional advanced features. A built-in data decompressor supports utilizing compressed PROM files, and design revisioning allows multiple design revisions to be stored on a single PROM or stored across several PROMs. For design revisioning, external pins or internal control bits are used to select the active design revision.

Multiple Platform Flash PROM devices can be cascaded to support the larger configuration files required when targeting larger FPGA devices or targeting multiple FPGAs daisy chained together. When utilizing the advanced features for the XCFxxP Platform Flash PROM, such as design revisioning, programming files which span cascaded PROM devices can only be created for cascaded chains containing only XCFxxP PROMs. If the advanced XCFxxP features are not enabled, then the cascaded chain can include both XCFxxP and XCFxxS PROMs.

See UG161 , Platform Flash PROM User Guide, for detailed guidelines on PROM-to-FPGA configuration hardware connections, for software usage, for a reference list of Xilinx FPGAs, and for the respective compatible Platform Flash PROMs. Table 2 lists the Platform Flash PROMs and their capacities.

Programming

The Platform Flash PROM is a reprogrammable NOR flash device (refer "Quality and Reliability Characteristics," page 14 for the program/erase specifications). Reprogramming requires an erase followed by a program operation. A verify operation is recommended after the program operation to validate the correct transfer of data from the programmer source to the Platform Flash PROM. Several programming solutions are available.

In-System Programming

In-System Programmable PROMs can be programmed individually, or two or more can be daisy-chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 3.

In-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The programming data sequence is delivered to the device using either Xilinx iMPACT software and a Xilinx download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The iMPACT software also outputs serial vector format (SVF) files for use with any tools that accept SVF format, including automatic test equipment. During in-system programming, the CEO Platform Flash PROM Configuration Bits 8,388,608 16,777,216 33,554,432 (b) DS123_33_031908 output is driven High. All other outputs are held in a high-impedance state or held at clamp levels during in-system programming. All non-JTAG input pins are ignored during in-system programming, including CLK, CE, CF, OE/RESET, BUSY, EN_EXT_SEL, and REV_SEL[1:0]. In-system programming is fully supported across the recommended operating voltage and temperature ranges.

Embedded, in-system programming reference designs, such as X APP058 , Xilinx In-System Programming Using an Embedded Microcontroller, are available on the Xilinx web page for P ROM Programming and Data Storage Application Notes . See UG161 , Platform Flash PROM User Guide, for an advanced update methodology that uses the Design Revisioning feature in the Platform Flash XCFxxP PROMs.

OE/RESET

The 1/2/4 Mb XCFxxS Platform Flash PROMs in-system programming algorithm results in issuance of an internal device reset that causes OE/RESET to pulse Low.

External Programming

In traditional manufacturing environments, third-party device programmers can program Platform Flash PROMs with an initial memory image before the PROMs are assembled onto boards. Contact a preferred third-party programmer vendor for Platform Flash PROM support information. A sample list of third-party programmer vendors with Platform Flash PROM support is available on the Xilinx web page for T hird-Party Programmer Device Support . See UG161 , Platform Flash PROM User Guide, for the PROM data file format required for programmers.

Pre-programmed PROMs can be assembled onto boards using the typical soldering process guidelines in UG112 , Device Package User Guide. A pre-programmed PROM’s memory image can be updated after board assembly using an in-system programming solution.

Reliability and Endurance

Xilinx in-system programmable products provide a guaranteed endurance level of 20,000 in-system program-erase cycles and a minimum data retention of 20 years. Each device meets all functional, performance, and data retention specifications within this endurance limit.

See UG116 , Xilinx Device Reliability Report, for device quality, reliability, and process node information.

Design Security

The Xilinx in-system programmable Platform Flash PROM devices incorporate advanced data security features to fully protect the FPGA programming data against unauthorized reading via JTAG. The XCFxxP PROMs can also be programmed to prevent inadvertent writing via JTAG. Table 3 and Table 4 show the security settings available for the XCFxxS PROM and XCFxxP PROM, respectively.

Read Protection

The read protect security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. Read protection does not prevent write operations. For the XCFxxS PROM, the read protect security bit is set for the entire device, and resetting the read protect security bit requires erasing the entire device. For the XCFxxP PROM the read protect security bit can be set for individual design revisions, and resetting the read protect bit requires erasing the particular design revision.

Write Protection

The XCFxxP PROM device also allows the user to write protect (or lock) a particular design revision or PROM option settings. Write protection helps to prevent an inadvertent JTAG instruction from modifying an area by write protecting the area and by locking the erase instruction. The write protection setting can be cleared by erasing the protected area. However, an XSC_UNLOCK instruction must first be issued to the XCFxxP PROM to unlock the ISC_ERASE instruction. Refer to the XCFxxP PROM BSDL file for the XSC_UNLOCK and ISC_ERASE instructions.