DAC3482EVM

EVAL MODULE FOR DAC3482

1 Introduction

1.1 Overview

This document is intended to serve as a basic user’s guide for the DAC3484/2 EVM Revision F, and DAC34H84/SH84 EVM revision C and above.

The Texas Instruments DAC348x evaluation module (EVM) is a family of circuit boards that allows designers to evaluate the performance of Texas Instruments' DAC348x family of digital-to-analog converters (DAC). The 16-bit, ultra low power family of DACs has either 16-bit wide or 32-bit wide DDR LVDS data input, integrated 2x/4x/8x/16x interpolation filters, 32-bit NCO, on-chip PLL, and exceptional linearity at high IFs. The EVM provides a flexible environment to test the DAC348x under a variety of clock, data input, and IF output conditions.

For ease of use as a complete IF transmit solution, the DAC348xEVM includes the Texas Instruments CDCE62005 clock generator/jitter cleaner for clocking the DAC348x. Besides providing a high-quality, low jitter DAC sampling clock to the DAC348x, the CDCE62005 also provides FPGA clocks to the TSW1400EVM (or TSW3100EVM) as FPGA reference clocks.

The EVM can be used along with Texas Instruments TSW1400 or TSW3100 with limited data rate support (up to 1.25GSPS LVDS Bus rate) to perform a wide varieties of test and measurements. The TSW1400 generates the test patterns that are fed to the DAC348x through a maximum 1.5 GSPS LVDS Bus port. These EVM boards are also compatible with Altera® and Xilinx® FPGA development platforms for rapid evaluation and prototyping. The on-board HSMC connector input allows direct connection to the HSMC compatible Altera development platforms, and the externally attached FMC-DAC-Adapter board available from TI enables the connection of the EVM to the Xilinx development platforms with FMC headers.

For evaluation of complete RF transmit solution, see the TSW308x EVM. The EVM integrates the DAC348x, TRF3705, and LMK04800 devices into one RF transmitter system.

1.2 EVM Block Diagram

Figure 1 shows the configuration of the EVM with the TSW1400 or TSW3100 used for pattern generation

2 Software Control

2.1 Installation Instructions

• Open folder named DAC348x_Installer_vxpx (xpx represents the latest version)

• Run Setup.exe

• Follow the on-screen instructions

• Once installed, launch the program by clicking on the DAC348x_GUI_vxpx program in Start>Texas Instruments DACs. The installation directory is located at C:\Program Files\Texas Instruments\DAC348x

• When plugging in the USB cable for the first time, you will be prompted to install the USB drivers.

– When a pop-up screen opens, select “Continue Downloading”.

– Follow the on screen instructions to install the USB drivers

– If needed, you can access the drivers directly in the install directory

2.2 Software Operation

The software allows programming control of the DAC device and the CDC device. The front panel provides a tab for full programming of each device. The GUI tabs provide more convenient and simplified interface to the most used registers of each device.

Each device, including the DAC3484, DAC3482, and DAC34H84/SH84, has its own custom control interface. At the top level of the GUI are five control tabs. The first four are used to configure the DAC348x and the last for the CDCE62005.

2.2.1 Input Control Options

• FIFO: allows the configuration of the FIFO and FIFO synchronization (sync) sources.

• LVDS delay: provides internal delay of either the LVDS DATA or LVDS DATACLK to help meet the input setup/hold time.

• Data Routing: provides flexible routing of the A, B, C, and D sample input data to the appropriate digital path.

Note: the DAC3482 does not support this mode

• SIF Control: provides control of the Serial Interface (3-wires or 4-wires) and Serial Interface Sync (SIF Sync).

• Input Format: provides control of the input data format (i.e., 2s complement or offset binary)

• Parity: provides configuration of the parity input.

• PLL Settings: provides configuration of the on-chip PLL circuitry.

• Temperature Sensor: provides temperature monitoring of DAC3484/2 die temperature.

2.2.1.1 FIFO Settings

The DAC348x has 8-samples deep FIFO to relax the timing requirement of a typical transmitter system. The FIFO has an input pointer and an output pointer, and both pointers can accept various input sources as reset triggers of input and output pointer position. One important application for input and output pointer control is the ability to synchronize multiple DACs in the system. For additional information, see the relevant DAC348x data sheet

• FIFO Offset: The default position of FIFO output pointer after reset by the synchronization source. This setting can be used to change the latency of the DAC348x.

• Data Formatter Sync (DAC3482 and DAC3484): Synchronization source for FIFO data formatter. Select between LVDS FRAME or LVDS SYNC signals.

• FIFO Sync Select (DAC34H84 and DAC34SH84): Select the internal digital routing of LVDS ISTR or LVDS SYNC to the FIFO ISTR path

• FIFO Input Sync: Synchronization source for FIFO input pointer. Select among the LVDS FRAME (ISTR), LVDS SYNC, and/or SPI register SIF-SYNC to reset the FIFO input pointer position.

• FIFO Output Sync: Synchronization source for FIFO output pointer. Select among the LVDS FRAME (ISTR), LVDS SYNC, SPI register SIF-SYNC, and/or OSTR signal to reset the FIFO output pointer position.

– For single device application without the need for precise latency control, Single Sync Source Mode may be used. The FIFO output pointer position can be reset with LVDS FRAME (ISTR), LVDS SYNC, and/or SPI register SIF-SYNC. See the Single Sync Source Mode in the relevant DAC348x data sheet for details.

– For multiple device synchronization, select the OSTR signal as the FIFO output synchronization source. If the DAC is configured to accept external DAC Clock input, then the OSTR signal is the external LVPECL signal to the OSTRP/N pins. If the DAC is configured to accept the internal onchip PLL clock, then the OSTR signal is the internally generated PFD frequency. See the Dual Sync Sources Mode in the relevant DAC348x data sheet for details.

2.2.1.2 LVDS Delay Settings

Depending on the signal source implementation (i.e. TSW1400, TSW3100, or FPGA System), the following options can be implemented to meet the minimum setup and hold time of DAC348x data latching:

• Set the on-chip LVDS DATA or DATACLOCK delay: The DAC348x includes on-chip LVDS DATA or DATACLK delay. The delay ranges from 0ps to 280ps with an approximate 40ps step. This LVDS DATACLOCK delay does not account for additional PCB trace-to-trace delay variation, only the internal DATACLK delay.

– The TSW1400 pattern generator sends out LVDS DATA and DATACLK as center aligned signal. Additional DATACLK delay is not needed.

– The TSW3100 pattern generator sends out LVDS DATA and DATACLK as edge-aligned signal. Typical setting of 160ps or more will help meet the timing requirement for most of the TSW3100 + DAC348x EVM setup.

• Modify the external LVDS DATACLK PCB trace delay: Additional trace length on the bottom side of the PCB can be added to the LVDS DATACLK PCB trace length. Set SJP9, SJP10, SJP11, and SJP12 to 2-3 position for approximately 220ps of trace delay.

2.2.1.3 PLL Settings

Follow the steps below to configure the PLL.

1. Enable PLL

2. Uncheck PLL reset and PLL sleep

3. Set M and N ratio such that FDAC = (M)/(N) x Fref

4. For the DAC3482, DAC3484, and DAC34H84: Set the prescaler such that the FDAC x prescaler is within 3.3GHz and 4GHz.

5. For the DAC34SH84, Set the prescaler such that the FDAC x prescaler is within 2.7GHz and 3.3GHz.

6. Set VCO Bias Tune to “1”

7. Charge Pump setting (a) If stability (P x M) is less than 120, then set to “Single”. (b) If stability (P x M) is greater than 120, then set to “Double” or install external loop filter

8. Adjust the Freq. Tune (coarse tune) accordingly. For additional information, see the relevant DAC348x data sheet