ADC3683EVM

ADC3683 DUAL-CHANNEL, 18-BIT, 65

Abstract

This user’s guide describes the characteristics, operation, and use of the ADC368x evaluation module (EVM). This user's guide discusses how to set up and configure the software and hardware, and reviews various aspects of the program operation. Throughout this document, the terms evaluation board, evaluation module, and EVM are synonymous with the ADC368xEVM. In the following sections of this document, the ADC368x evaluation board is referred to as the EVM and the ADC368x devices are referred to as the ADC devices, respectively. This document applies only to the ADC3683EVM and ADC3682EVM.

1 Introduction

The ADC36xxEVM is an evaluation board used to evaluate the ADC368x analog-to-digital converters (ADC) from Texas Instruments. The ADC368x uses a serial LVDS interface to output the digital data. The serialized LVDS interface supports output rates to 1 Gbps. The ADC368x can be operated in 'oversampling + decimating' mode using the internal decimation filter in order to improve the dynamic range and relax external anti-aliasing filter.

The ADC368xEVM is equipped with the following features:

• Transformer and FDA coupled analog inputs

• CDCE6214 clocking solution for on-board clocking

• Transformer coupled or single-ended clock inputs

• INA226 current shunt monitors for evaluating power consumption

• Power over mini-USB

• FMC connector

By default, the EVM is configured to receive external inputs for the sampling clock and analog input via AC coupled, transformer (balun) inputs. These transformers perform single-ended to differential conversion, and provide a low noise/distortion passive input.

To exercise the full performance capabilities of this high performance SAR ADC, it is recommended to evaluate the ADC in the default configuration, and then evaluate in other configurations (like onboard clocking or FDA input), as required.

2 Equipment

This hardware setup procedure is written with the intent to use external clocking (sample clock and DCLKIN) and transformer coupled analog inputs. Using onboard clocking and FDA driven analog inputs is an option, and instructions are provided toward the end of this document to make the required hardware/software modifications.

2.1 ADC368xEVM Functionality

The ADC368xEVM receives power from the USB 2.0, +5 V rail, and is then converted to +3.3 VDC and +1.8 VDC. The ADC receives +1.8 VDC from the TPS62231 DC-DC converter. The power consumption of the 1.8 V rail can be monitored (using the INA226) in the ADC35xxEVM GUI. USB-to-SPI communication is established using the FTDI (FT4234H). The ADC clocks can be supplied externally or from the onboard PLL/Distributor CDCE6214 (high quality external clocks are used to acheive best AC performance). The analog input can be AC coupled through the Balun (ADT1-6T+) input, or DC (or AC) coupled with the onboard FDA (THS4541). The analog input is 3.2 Vpp, and is driven a -1 dBFS (~2.8 Vpp) in all examples in this user's guide.

The ADC368x family has a +1.6 V voltage reference (VREF), and can be supplied internally or externally. By default, the EVM is configured to supply an external voltage reference using the REF3318 (divided down to +1.6V) and the OPA837 high speed amplifier to drive the voltage reference. At any time, the VREF can be changed to internal reference by SPI write.

The ADC368x family uses an unbuffered analog input, so a glitch filter is required to attenuate the ADC sampling glitch from when the sampling capacitors switch (sample/hold). The glitch filter acts as a low pass filter with an corner frequency (Fc) at 30 MHz (accepts DC to 30 MHz).

The ADC368xEVM LVDS output data is routed to an FMC connector, and then connected to the LVDS Interposer card. This interposer card then maps to the TSW1400EVM's HSMC connector in order to capture the ADC368xEVM SLVDS clock and data signals.