LP38502ASD-EV

BOARD EVAL FOR LP38502ASD

1    Introduction

The LP38502ASD-ADJ is a 1.5A low-dropout (LDO) linear regulator in the LLP-8 package that has an adjustable output voltage (set by external resistors).

2    Basic Application Circuit

The basic application circuit that is built up on the evaluation board is shown in Figure 1.

3    Changing the Output Voltage

The resistors R1 and R2 set the output voltage. Equation 1 determines output voltage: VOUT = VADJ x (1 + R1/R2) where VADJ is typically 0.6 V. The board has installed values of: R1 = 19.1 kΩ (1) R2 = 6.04 kΩ which sets the output to 2.5 V. R1 can be adjusted to change the nominal output voltage to other values. The minimum output voltage that can be set is the ADJ pin voltage, which is approximately 0.6 V. This is obtained by installing a jumper or low value resistor (less than 10 Ω) at R1. The maximum usable output voltage is limited by the maximum input voltage, which is 5.5 V. Since rated dropout voltage at full current is 0.375 V, this means the maximum usable output voltage for full current operation is about 5.1 V

4.    Feedforward Capacitor C2

The PCB layout includes a location for C2, which is a feedforward capacitor connected across R1. If the data sheet guidelines are followed, and R2 does not exceed 10 kΩ, C2 is not required and has no effect on performance. The internal compensation is such that an internal zero provides more than adequate phase margin so external compensation is never needed.

However, if the value of R2 is increased above 10 kΩ, the effect of the internal zero gradually diminishes and the phase margin is reduced. At an R2 value of approximately 50 kΩ, the phase margin will be low enough that instability may occur. In such cases, some of the lost phase margin can be regained by placing a capacitor at C2. Although it is sometimes possible to regain adequate phase margin this way, it is recommended that the data sheet guidelines be followed and R2 not exceed 10 kΩ (so C2 is never required).

5    Power Dissipation

The power dissipated within the regulator IC is given by: PD = IL (VIN- VOUT ) Where: PD is the power dissipated in the IC regulator U1. IL is the load current. (2) VIN is the value of VIN measured at TP2 (not at J1). VOUT is the value of VOUT measured at TP5 (not at J4).

The thermal resistance of U1 from junction to ambient can be assumed to be approximately 80°C/W for this assembly. That means that the junction temperature will rise about 80°C above ambient for each Watt of power dissipated within the IC.

The parametric specifications of the IC are for a maximum junction temperature of 125°C, and the maximum allowable junction temperature is 150°C. This limits maximum usable power dissipation for this package to approximately 1.5W. If power dissipation exceeds this (and the junction temperature approaches 150°C), the part may go into thermal shutdown.

6     PCB Component Layout

The components listed in the basic application circuit can be identified using the silkscreen on the top layer of the PCB (see Figure 2).